1. Field of the Invention
The present invention relates generally to nonvolatile semiconductor memory devices and, more particularly, to a nonvolatile semiconductor memory device in which data can electrically be written and erased.
2. Description of the Background Art
There are two types of semiconductor memory devices: the one is a volatile memory such as a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory) and the like, and the other is a nonvolatile memory. Storage data of a volatile memory are all erased when a power supply is OFF. Storage data of a nonvolatile memory are, however, not erased even if the power supply is OFF. As a representative of nonvolatile semiconductor memory devices, there is a PROM (programmable read only memory). The PROM is a semiconductor memory device in which information is written by a user. As one type of the PROM, there is an EEPROM (electrically erasable and programmable ROM) in which written information can electrically be erased so that information can be rewritten any times. An EEPROM in which storage data of all memory cells can be erased in block is called a flash EEPROM.
FIG. 21 is a schematic block diagram showing a fundamental structure of a conventional flash EEPROM. With reference to FIG. 21, the flash EEPROM includes a memory array 1, a row decoder 4, a Y gate 2 and a column decoder 5.
Memory array 1 includes a plurality of memory cells MC arranged in matrix in the directions of rows and columns. Each of memory cells MC is connected to a corresponding bit line 30 and a corresponding word line 50 in memory array 1. A FAMOS (floating-gate avalanche injection MOS) transistor capable of storing charges in a floating gate is employed in each memory cell MC.
FIG. 22 is a cross-sectional view showing structure of a FAMOS transistor. With reference to FIG. 22, the FAMOS transistor includes a control gate 200, a floating gate 210, N type regions 220 and 230 formed on a P type substrate 240, and an insulator layer 250. Floating gate 210 is formed on P type substrate 240 to bridge N type regions 220 and 230, with insulator layer 250 interposed therebetween. Control gate 200 is formed on floating gate 210 with insulator layer 250 interposed therebetween. Control gate 200 and floating gate 210 are both formed of polysilicon. Insulator layer 250 is formed of an oxide film such as SiO.sub.2 or the like. Oxide film 250 formed between P type substrate 240 and floating gate 210 has such a small thickness as of normally approximately 100 .ANG.. Control gate 200 is connected to a corresponding word line 50 in FIG. 21. The one N type region 220 of the two N type regions is connected as a drain of this MOS transistor to a corresponding bit line 30 in FIG. 21. The other N type region 230 is connected as a source of the MOS transistor to a source line 80 which is common to all memory cells MC in FIG. 21. P type substrate 240 is grounded.
In data writing, high voltage pulses of 12 V or less are applied to control gate 200 and drain 220 via word line 50 and bit line 30, respectively. Source 230 is grounded via source line 80. When the high voltage pulses are applied to drain 220, and source 230 is grounded, avalanche breakdown is caused, so that hot electrons are generated in the vicinity of the interface between drain 220 and P type substrate 240. Accordingly, an electric current flows in drain 220. Since the high voltage pulses are also applied to control gate 200, the hot electrons .crclbar. are accelerated by an electric field from control gate 200 and then injected into floating gate 210 through thin oxide film 250 formed between floating gate 210 and P type substrate 240.
The electrons injected into floating gate 220 cannot escape therefrom because floating gate 210 is electrically insulated by oxide film 250. Thus, the electrons once injected into floating gate 210 do not leak out from floating gate 210 but stored therein for a long time even after a power supply is cut off. The state where the electrons are stored in floating gate 210 corresponds to data "0", and the state where no electrons are stored in floating gate 210 corresponds to data "1". Therefore, storage data of memory cells MC are held even after the power supply is cut off. If the electrons are stored in floating gate 210, a threshold voltage of the MOS transistor is raised due to the electric field from the stored electrons. That is, no inversion layer is produced in a channel region unless control gate 200 is supplied with a higher voltage than the voltage enabling an inversion layer to be formed in the channel region when no electrons are stored in floating gate 210.
In erasing of the storage data, a high voltage is applied to source 230 via source line 80, and control gate 200 is grounded via word line 50. This causes a high electric field having a higher potential on source 230 to be applied to a portion between floating gate 210 and source 230. As a result, a tunnel phenomenon occurs in oxide film 250 insulating floating gate 210 and source 230 from each other, so that a current (tunnel current) flows between floating gate 210 and source 230. That is, the electrons leak out from floating gate 210 to source 230 through oxide film 250. Accordingly, the electrons stored in floating gate 210 are removed, so that the threshold voltage of the MOS transistor is lowered. Since source line 80 is commonly connected to respective sources of memory cells MC, as shown in FIG. 21, the storage data of all memory cells MC in memory array 1 are erased in block.
In data reading, control gate 200 and drain 220 are supplied with a supply voltage (normally 5 V) and a voltage relatively close to the supply voltage via corresponding word line 50 and bit line 30, respectively. Source 230 is grounded via source line 80. If no electrons are stored in floating gate 210 (i.e., if storage data is "1"), the threshold voltage of the MOS transistor is low, so that a channel is produced between source 230 and drain 220 in response to the supply voltage applied to control gate 200. If the electrons are stored in floating gate 210 (i.e., if storage data is "0"), however, the threshold voltage of the MOS transistor is high, so that no channel occurs between source 230 and drain 220 even if the supply voltage is applied to control gate 200. Accordingly, the MOS transistor constituting the memory cell, in which the storage data is "1", is turned on in data reading, so that a current flows from corresponding bit line 30 to source line 80. Since the MOS transistor constituting the memory cell, in which the storage data is "0", is in an OFF state even in data reading, no current flows from corresponding bit line 30 to source line 80. Thus, in data reading, a sense amplifier detects whether or not the current flows through a bit line corresponding to the memory cell, from which data is to be read. A determination is made as to whether the storage data is "1" or "0", based on a result of this detection.
If a potential to be applied to bit line 30 in data reading is too high, a high electric field is applied to oxide film 250 formed between floating gate 210 and drain 220, and hence the electrons stored in floating gate 210 are drawn to the drain 220 side. Thus, the potential to be applied to bit line 30 is approximately 1-2 V. Therefore, a small current flows through the memory cell, in which the storage data is "1" in data reading. Thus, a current sense amplifier is employed to detect this small current.
With reference to FIG. 21 again, address input terminals A0-AK receive an externally applied address signal. This address signal serves to instruct which one of memory cells MC in memory array 1 data is to be read from or written in. An address buffer 6 buffers an applied address signal to apply the buffered address signal to a row decoder 4 and a column decoder 5.
An input/output buffer 9 is connected to input/output terminals I/O.sub.0 -I/O.sub.N for receiving input data and output data. Input/output buffer 9 applies write data which is externally applied to input/output terminals I/O.sub.0 -I/O.sub.N to a write circuit 7. Further, input/output buffer 9 provides data supplied from a sense amplifier 8 to input/output terminals I/O.sub.0 -I/O.sub.N as read data.
Write circuit 7 supplies a voltage corresponding to the write data applied from input/output buffer 9 to a Y gate 2. Sense amplifier 8 detects an output of Y gate 2 and, in response to a result of the detection, supplies a signal voltage corresponding to data "0" or "1" as read data to input/output buffer 9.
Row decoder 4 responds to the address signal from address buffer 6 to select one of word lines 50 in memory array 1. Column decoder 5 responds to the address signal from address buffer 6 to select one of bit lines 30 in memory array 1.
A control circuit 140 controls Y gate 2, column decoder 5, write circuit 7, address buffer 6, input/output buffer 9 and sense amplifier 8 so that they can perform an operation corresponding to each mode.
A terminal T.sub.PP is supplied with an external high voltage V.sub.PP. A terminal T.sub.CC is supplied with an external supply voltage V.sub.CC of a normal level. A switch circuit 400 selectively outputs to predetermined circuitry one of the high voltage V.sub.PP and supply voltage V.sub.CC applied respectively to terminals T.sub.PP and T.sub.CC.
Switch circuit 400 is controlled by control circuit 140 to supply the high voltage V.sub.PP from terminal T.sub.PP to row decoder 4 in data writing. Further, switch circuit 400 is controlled by control circuit 140 to apply the supply voltage V.sub.CC to row decoder 4 in data reading. Switch circuit 400 is further controlled by control circuit 140 to supply the high voltage V.sub.PP to a source line switch 3 in data erasing.
In data writing, Y gate 2 supplies the voltage applied from write circuit 7 to a bit line selected by column decoder 5. Specifically, if write data is "0", Y gate 2 supplies the high voltage V,, to the selected bit line. If the write data is "1", Y gate 2 holds a potential on the selected bit line at a ground potential. In data writing, row decoder 4 supplies the high voltage V.sub.PP from high voltage switch circuit 400 to a selected word line. In data writing, source line switch 3 applies the ground potential to source line 80. Therefore, if the write data is "0", the electrons generated by avalanche breakdown are injected only into floating gate 210 of a memory transistor (a selected memory transistor) located at the cross-over point between the word line selected by row decoder 4 and the bit line selected by column decoder 5. If the write data is "1", however, no electrons are injected into floating gate 210 since the voltage of control gate 200 is not boosted in the selected memory transistor.
In data reading, row decoder 4 supplies a supply voltage V.sub.CC applied from switch circuit 400, which is lower than the above-described high voltage V.sub.PP, to the selected word line. In data writing, Y gate 2 supplies a low voltage of 1-2 V to the bit line selected by column decoder 5. In data reading, source line switch 3 applies a ground potential to source line 80 like the case in data writing. Accordingly, if storage data of the selected memory transistor is "1", a current flows from the selected bit line through drain 220, the channel region and source 230 of the selected memory cell to source line 80. If the storage data of the selected memory transistor is "0", the selected memory transistor is not turned on in response to a gate voltage of approximately 5 V, so that no current flows through the selected bit line. Y gate 2 supplies a supply voltage to the selected bit line and also electrically connects only the selected bit line to sense amplifier 8. This enables sense amplifier 8 to detect whether the current flowing through the selected bit line exists or not.
In data erasing, Y gate 2 maintains all bit lines 30 in memory array 1 at a lower potential (ground potential). Row decoder 4 supplies the ground potential to all word lines 50 in memory array 1, in data erasing. Source line switch 3 converts the high voltage V.sub.PP applied from switch circuit 400 into a pulse signal, to apply the pulse signal to source line 80. Therefore, in data erasing, a tunnel phenomenon occurs in each of all memory cells MC in memory array 1, so that the electrons stored in floating gate 210 of the memory transistor, in which the storage data is "0", are removed from floating gate 210. Accordingly, when the data erasing is completed, the storage data of all memory cells MC in memory array 1 are "1".
It is assumed in the following description that the supply potential and the ground potential correspond to a logic high level (or the H level) and a logic low level (or the L level), respectively.
As described in the foregoing, in the EEPROM, data erasing is carried out by forcing the bending of an energy band between floating gate 210 and source 230 so as to make electrons to tunnel from floating gate 210 to source 230, with a high voltage applied between control gate 200 and source 230 of the memory transistor in data erasing. Thus, the amount of electrons drawn out from floating gate 210 varies depending on the magnitude of a high voltage to be applied to source line 80, the time period in which the high voltage is applied (i.e., the pulse width of high voltage pulses), the thickness of oxide film 250 existing between floating gate 210 and source 230, the thickness of oxide film 250 existing between floating gate 210 and control gate 200, and the like.
There are irregularities in manufacture of memory transistors constituting memory array 1. Because of the irregularities, the thickness of oxide film 250, the form of control gate 200 and floating gate 210, the length of the channel region, and the like are not completely uniformed in all memory transistors. It is actually difficult to simultaneously set the storage data of all memory cells MC in memory array 1 to "1" by the above-described collective erasing, due to the irregularities on manufacture of the memory transistors and other various factors such as some causes in actual circuit configurations. More specifically, in some of the memory transistors, in which the storage data is "0", only the stored electrons are completely removed from floating gate 210 in response to a high voltage applied in collective erasing, whereas in the other memory transistors, a larger amount of electrons than those stored in data writing are drawn out from floating gate 210 in response to the high voltage applied in collective erasing. The phenomenon of the latter case, in which the electrons are excessively drawn out from the floating gate, is called an excess erase.
When an excess erase occurs, floating gate 210 is charged to plus, so that an inversion layer is produced between source 230 and drain 220. This means that this memory transistor is in an ON state even if any potential of 0 V or more is applied to control gate 200. As a result, in data reading, a current flows through a bit line corresponding to this memory transistor despite the fact that the transistor is in a non-selection state. Thus, if a memory cell connected to the bit line corresponding to the memory transistor subjected to the excess erase is selected, read data is "1" even in case where storage data of the selected memory transistor is "0". In data writing, if data "0" is intended to be written in the excess-erased memory cell or the memory cell connected to the same bit line as that of the excess-erased memory cell, a current flows not only through the selected memory cell but also the excess-erased memory cell, so that sufficient avalanche breakdown is not generated in the selected memory cell. Thus, electrons are not sufficiently injected into floating gate 210 of the selected memory cell. Accordingly, if the excessively erased memory cell exists, writing characteristics in data writing deteriorate, and further, data writing is disabled. As described above, the excess erase causes troubles in data reading and data writing.
In order to prevent such an excess erase, the following method is adopted at present. That is, the pulse width of a high voltage pulse (hereinafter referred to as erase pulse) to be applied to source line 80 for data erasing is made smaller. Every time this erase pulse having the shorter pulse width is applied to source 80 once, the storage data of all the memory cells in memory array 1 are read, so as to check whether or not all the storage data of memory cells MC in memory array 1 are "1". If there is even one memory cell in which the storage data is not "1", the erase pulse of the shorter pulse width is again applied to source line 80. The confirmation as to whether or not the storage data of the memory cells are "1" after the erase pulse is applied to source line 80, i.e., whether or not the storage data of the memory cells are completely erased, is called erase verifying. Such erase verification and such application of the erase pulse to source line 80 are repeated until the data erasing is completed with respect to all memory cells MC in memory array 1. FIG. 23 is a block diagram showing configuration of a flash EEPROM in which an excess erase is prevented by such a method. This flash EEPROM is stated in ISSCC Digest of Technical Papers (1990), pp. 60-61 and Electronic Information Communication Society Technical Research Papers (May 21, 1990), pp. 73-77.
With reference to FIG. 23, this flash EEPROM includes an erase control circuit 11 for performing erase verification. Erase control circuit 11 is connected to a source line switch 3, a row decoder 4, a column decoder 5, an address buffer 6, a sense amplifier 8 and a mode control circuit 10. An internal configuration of erase control circuit 11 is shown in detail in FIG. 24. FIG. 25 is a circuit diagram showing the structure of a memory array 1 and Y gate 2 and the connecting relation between memory array 1 and Y gate 2 and peripheral circuits in case where memory array 1 includes 9 memory transistors arranged in matrix of 3 rows and 3 columns by way of example. FIG. 26 is a timing chart showing an operation of this flash EEPROM in data erasing. A description will now be made of the structure and operation of the flash EEPROM mainly in data erasing, with reference to FIGS. 24-26.
With reference to FIG. 24, erase control circuit 26 includes a command signal latch circuit 112, a sequence control circuit 113, a verify voltage generator 114 and a voltage switch 115. Command signal latch circuit 112 receives only a status polling command signal of control signals to be applied from mode control circuit 10, the signal indicating that this flash EEPROM enters in an erase mode. Sequence control circuit 113 is circuitry for controlling the generation of erase pulses and a circuit operation for erase verifying. Verify voltage generator 114 supplies a voltage of 3.4 V lower than a normal supply voltage of 5 V to voltage switch 115. In data writing, voltage switch 115 changes a high voltage V.sub.PP (=12 V; FIG. 1(b)) to be supplied to a selected word line and a selected bit line, normal supply voltage V.sub.CC (=5 V; FIG. 26(a)) and the voltage of 3.4 V to be supplied from verify voltage generator 114, in data writing, normal data reading and erase verifying, so as to output those changed voltages as outputs. The outputs of voltage switch 115 are applied to row decoder 4, column decoder 5 and sense amplifier 8.
Sequence control circuit 113 includes an address counter 116, an erase/erase verifying control circuit 117, a decoder control circuit 119 and an erase pulse generator 118. Address counter 116 is controlled by command signal latch circuit 112 and erase/erase verifying control circuit 117 so as to output address signals, sequentially designating the memory cells in memory array 1 in the order of address, to address buffer 6 in a data erase mode. Erase/erase verifying control circuit 117 is controlled by command signal latch circuit 112 so as to control verify voltage generator 114, address counter 116, decoder control circuit 119 and erase pulse generator 118 in response to read data applied from sense amplifier 8. Erase pulse generator 118 is controlled by erase/erase verifying control circuit 117 so as to supply, if necessary, erase pulses having a pulse width 10 msec to source line switch 3. Decoder control circuit 119 is controlled by mode control circuit 10 and erase/erase verifying control circuit 117, to instruct row decoder 4 to output a voltage of a logic low level only during the period when erase pulses are generated from erase pulse generator 118.
Mode control circuit 10 performs a mode setting of this flash EEPROM in response to external control signals such as an erase enable signal EE, a chip enable signal CE, an output enable signal OE, a program signal PGM and the like. Erase enable signal EE is a control signal for enabling/disabling an erasing operation of the flash EEPROM. Chip enable signal CE is a control signal for enabling/disabling an operation of this flash EEPROM chip. Output enable signal OE is a control signal for enabling/disabling a data output operation of the flash EEPROM. Program signal PGM is a control signal for enabling/disabling a data writing operation of the flash EEPROM. All of these erase enable signal EE, chip enable signal CE, output enable signal OE and program signal PGM are low active signals. More specifically, erase enable signal EE designates the enabling of an erasing operation when it is at a logic low level. Conversely, this signal designates the disabling of the erasing operation when it is at a logic high level. Chip enable signal CE also designates the enabling of a chip operation only when it is at a logic low level. Output enable signal OE also designates the enabling of a signal output operation only when it is at a logic low level. Program signal PGM also designates the enabling of a writing operation only when it is at a logic low level.
With reference to FIG. 26, when chip enable signal CE (FIG. 26(d)) is at a logic low level and thus this flash EEPROM chip is enabled, the flash EEPROM enters in the erase mode if erase enable signal EE (FIG. 26(g)) is held at a logic low level for a definite time period t.sub.EW (=50 nsec). At this time, output enable signal OE (FIG. 26(e)) and program signal PGM (FIG. 26(f)) both attain a logic high level so that externally applied data may not be written in memory array 1, and storage data of memory array 1 may not be read out to the outside. Mode control circuit 25 detects that erase enable signal EE attains a logic low level for the definite period t.sub.EW when output enable signal OE and program signal PGM are both at a logic high level and chip enable signal CE is at a logic low level. In response to this detection, mode control circuit 10 outputs a signal designating the erase mode to command signal latch circuit 112 and decoder control circuit 119.
In the erase mode, data "0" is first written in all the memory cells in memory array 1. A circuit operation for this writing will now be described.
When the erase mode is designated by mode control circuit 10, command signal latch circuit 112 latches an erase mode designating output of mode control circuit 10 and also applies this output to address counter 116 and erase/erase verifying control circuit 117. Address counter 116 responds to the erase mode designating output to start a counting operation to generate an address signal (FIG. 26(c)). Address counter 116 outputs an address signal indicating a subsequent address to the address indicated by the address signal that has been output so far, every time a count value thereof is incremented by one. Thus, the address signal is output from address counter 116 while being incremented each definite time. In the erase mode, address buffer 6 accepts the address signal generated from address counter 116 to apply the same to row decoder 4 and column decoder 5. Erase/erase verifying control circuit 117 responds to the applied erase mode designating output to control row decoder 4, column decoder 5 and write circuit 7. Row decoder 4 is controlled by erase/erase verifying control circuit 117 so as to select a single word line in memory array 1 in response to the address signal accepted by address buffer 6. Column decoder 5 is controlled by erase/erase verifying control circuit 117 so as to select a single bit line in memory array 1 in response to the address signal accepted by address buffer 6.
A description will now be made on the internal structure of memory array 1 and Y gate 2. With reference to FIG. 25, memory transistors MC are each provided in the corresponding cross-over points between word lines WL1-WL3 connected to row decoder 4 and bit lines BL1-BL3 connected to Y gate 2. Each of memory transistors MC has the structure shown in FIG. 22. Respective sources of all memory transistors MC are commonly connected to source line 80 connected with source line switch 3. Y gate 2 includes an I/O line 27 connected to write circuit 7 and sense amplifier 8, and N channel MOS transistors TR1-TR3 provided as transfer gates between I/O line 27 and bit lines BL1-BL3, respectively. Respective gates of transistors TR1-TR3 are connected via different connecting lines Y1-Y3 to column decoder 5. As described above, connecting lines Y1-Y3 each correspond to bit lines BL1-BL3 in the correspondence of one to one.
Row decoder 4 responds to an applied address signal to selectively output a high voltage V.sub.PP to any one of word lines WL1-WL3 in memory array 1. Column decoder 5 responds to an applied address signal to selectively apply a voltage of a logic high level to only one of connecting lines Y1-Y3 in Y gate 2. Accordingly, only one of transfer gates TR1-TR3, which is provided corresponding to the selected connecting line, is turned on, so that only one of bit lines BL1-BL3 corresponding to the selected connecting line is electrically connected to I/O line 27.
Write circuit 22 is controlled by erase/erase verifying control circuit 117 so as to apply a high voltage V.sub.PP to I/O line 27. I/O line 27 is electrically connected only to the bit line selected by column decoder 5. Thus, the high voltage V.sub.PP applied to I/O line 27 is applied only to the selected bit line (one of bit lines BL1-BL3). Source line switch 3 supplies a ground potential to source line 80.
As the result of such a circuit operation, electrons caused by avalanche breakdown are injected into the floating gate only in one memory transistor of memory transistors MC in memory array 1, corresponding to the address signal generated by address counter 116. The address signal applied to address buffer 6 is kept incremented by the counting operation of address counter 11 until all memory transistors MC in memory array 1 are selected. Thus, a selecting operation of row decoder 4 and column decoder 5 brings memory transistors MC in memory array 1 sequentially into a selection state in the order of address, so that the electrons are injected into the floating gate of each memory transistor. As a result, data "0" is written in all memory cells 30 in memory array 1. If the address signal supplied as an output from address counter 116 is incremented up to a final value, the data writing into memory array 1 is completed. With the data writing completed, a circuit operation for data erasing starts. A description will now be made on the circuit operation for data erasing.
First, erase/erase verifying control circuit 117 instructs erase pulse generator 118 to generate erase pulses. In response to this instruction, erase pulse generator 118 applies high voltage pulses having a predetermined pulse width of 10 msec as erase pulses to source line switch 3. Source line switch 3 applies the applied erase pulses to source line 80 of FIG. 25.
At the same time, erase/erase verifying control circuit 117 applies a signal instructing decoder control circuit 119 to start an erasing operation. In response to the applied signal, decoder control circuit 119 supplies as an output a control signal for forcing all outputs of row decoder 4 to attain a logic low level during the period when the decoder control circuit is receiving the erase pulses from erase pulse generator 118. Accordingly, word lines WL1-WL3 of FIG. 25 are supplied with a potential of a logic low level during the period when source line 80 is supplied with high voltage pulses. As a result, the tunnel phenomenon, in which the electrons injected into the floating gate in data writing are drawn out through the insulator layer to the source region, occurs in each of memory transistors MC in memory array 1.
When the application of the high voltage pulses to source line 80 is completed, a verification is made as to whether or not data "0" of all memory cells MC in memory array 1 are erased, according to the application of the high voltage pulses. That is, an erase verifying is carried out. A description will now be given of a circuit operation in erase verifying.
When the generation of the high voltage pulses from erase pulse generator 118 is completed, erase/erase verifying control circuit 117 instructs address counter 116 to start a counting operation and also instructs decoder control circuit 119 to start an erase verifying operation. Further, erase/erase verifying control circuit 117 instructs verify voltage generator 114 to generate/output a voltage of 3.4 V. Address counter 116 generates an address signal in response to the instruction from erase/erase verifying control circuit 117. Decoder control circuit 119 responds to the instruction from erase/erase verifying control circuit 117 to output a control signal for operating row decoder 4 and column decoder 5 in the same manner as in normal data reading. Verify voltage generator 114 responds to the instruction from erase/erase verifying control circuit 117 to supply the voltage of 3.4 V to voltage switch 115.
The address signal generated from address counter 116 is accepted by address buffer 6, to be applied to row decoder 4 and column decoder 5. Voltage switch 115 supplies the voltage of 3.4 V applied from verify voltage generator 114 to row decoder 4 and sense amplifier 8.
Row decoder 4 is controlled by decoder control circuit 119 to supply the voltage of 3.4 V applied from voltage switch 115 to only a single word line of word lines WL1-WL3 in memory array 1, corresponding to the address signal applied from address buffer 6, and hold potentials on the other word lines at a logic low level. Accordingly, the voltage of 3.4 V is applied to the respective control gates of all the memory transistors connected to the selected word line in memory array 1. Column decoder 5 is controlled by decoder control circuit 119 to supply a voltage of a logic high level to only one of connecting lines Y1-Y3 in Y gate 2, corresponding to the address signal applied from address buffer 6, and hold potentials on the other connecting lines at a logic low level. Thus, only one of transfer gates TR1-TR3, corresponding to the selected connecting line, is turned on in Y gate 2. As a result, only the selected bit line of bit lines BL1-BL3 is electrically connected to I/O line 27. Sense amplifier 8 is driven at the voltage of 3.4 V applied from voltage switch 115 to detect a current flowing through I/O line 27. Source line switch 3 grounds source line 80 when no erase pulses are applied from erase pulse generator 118. Thus, in erase verifying, the respective voltages of 3.4 V and 0 V are applied to the control gate and the source of the selected memory transistor in memory array 1.
If no electrons are stored in the floating gate of the selected memory transistor, i.e., if the threshold voltage of the selected memory transistor is lower than a predetermined value, the selected memory transistor is rendered conductive in response to the voltage of 3.4 V applied from row decoder 4. Thus, a current flows from I/O 27 via the selected transfer gate and the selected bit line to source line 80. The predetermined value is set for an average threshold voltage of the memory transistors, in which no data is written. Therefore, if the electrons stored in the floating gate of the selected memory transistor in data writing are completely removed in response to the foregoing erase pulses, the current flows through the selected bit line. If the electrons remain in the floating gate of the selected memory transistor, however, the threshold value of the selected transistor does not fall down to the predetermined value. Thus, the selected memory transistor is not rendered conductive in response to a gate voltage of 3.4 V applied from row decoder 4, so that no current flows through the selected bit line. Thus, if storage data of the selected memory cell is completely erased, a current flows through I/O line 27. Conversely, if the storage data of the memory cell is not completely erased, no current flows through I/O line 27.
Sense amplifier 8 operates in the same manner as in normal data reading, so as to make a determination, based on the presence/absence of the current flowing through I/O line 27, as to whether or not a current flows through the selected bit line. If no current flows through the selected bit line, then sense amplifier 8 applies a signal corresponding to data "0" as read data to erase/erase verifying control circuit 117. Conversely, if a current flows through the selected bit line, sense amplifier 8 applies a signal corresponding to data "0" as read data to erase/erase verifying control circuit 117. Erase/erase verifying control circuit 117 responds to the data applied from sense amplifier 8 being "1" to instruct address counter 116 to increment an address signal. Also, this erase/erase verifying control circuit 117 successively controls verify voltage generator 114 and decoder control circuit 119 in the same manner as so far. Further, this control circuit 117 responds to the data read by sense amplifier 8 being "0" to control erase pulse generator 118 and decoder control circuit 119 like in the previous erase pulse application so that all word lines WL1-WL3 in memory array 1 may be grounded by row decoder 4 and high voltage pulses may be applied to source line 80.
Therefore, if the storage data of the selected memory cell is "1", i.e., if the electrons are completely removed from the floating gate of the selected memory transistor, the address signal generated from address counter 116 is incremented. Then, the storage data of the memory cell corresponding to the incremented address signal is read by sense amplifier 8. Conversely, if the storage data of the selected memory cell is "0", i.e., if the electrons are not completely removed from the floating gate thereof, erase pulses are again applied to all memory transistors MC in memory array 1. As described above, erase/erase verifying control circuit 117 selectively performs, in the erase mode, a control operation for reading data from a new memory cell or a control operation for applying erase pulses again to memory array 1, in response to each of read data applied from sense amplifier 8 after data writing. More specifically, erase/erase verifying control circuit 117 detects the memory cell, in which no data is erased, based on an output of sense amplifier 8 and, in response to this detection, circuit 117 again generates the erase pulses.
Specifically, if the first erase pulse is applied to memory array 1, erase/erase verifying control circuit 117 does not instruct the re-generation of another erase pulse so far as read data applied from sense amplifier 8 is not "0". Thus, data is read in the order of address from memory array 1 after the first erase pulse application until the data read by sense amplifier 8 is "0". Then, when the read data is "0", the second erase pulse is applied to memory array 1 by the control operation of erase/erase verifying control circuit 117. Data is again read from memory array 1 after the second erase pulse application. At this time, since an address signal generated from address counter 116 is not incremented, the data, which is first read after the second erase pulse application, is storage data of the previous memory cell, in which the read data is "0" after the first erase pulse application. If the storage data of this memory cell attains "1" in response to the second erase pulse, erase/erase verifying control circuit 117 increments the address signal, so that data is read from the next address 1. If the data of this memory cell is still "0" even after the second erase pulse application, however, the third erase pulse is applied to memory array 1 by the control operation of erase/erase verifying control circuit 117.
As in the foregoing manner, after the first erase pulse is applied to memory array 1, the storage data of the memory cell is sequentially read in the order of address, and the data reading is interrupted at the time when the memory cell, in which the data is not completely erased in response to the first erase pulse, is detected. Then, erase pulses are repetitively applied to memory array 1 until the storage data of this detected memory cell is "1". As a result, when the storage data of the detected memory cell is completely erased, the data reading restarts with an address next to the address of the detected memory cell. Then, such a circuit operation is repeated every time the data to be read is "0" so that the memory cell, in which the data is not completely erased, is detected. Thus, such a process that the address generated from address counter 116 is incremented to a maximal value, so that the reading of data from all memory cells MC in memory array 1 is completed means that the storage data of all memory cells MC in memory array 1 are completely erased.
If the data reading from all memory cells MC is completed, erase/erase verifying control circuit 117 resets latch data of command signal latch circuit 112. The signal latched in command signal latch circuit 112 is output as a status signal. Accordingly, it can be recognized based on a potential of input/output terminal I/O 7 whether or not a circuit operation for data erasing (the application of erase pulses and the erase verifying operation) continues. Specifically, with reference to FIG. 26, after erase enable signal EE attains a logic low level for a definite period t.sub.EW to enter in the erase mode, chip enable signal CE attains a logic low level so as to enable the operation in response to an external signal of this flash EEPROM. Further, output enable signal OE attains a logic low level so as to enable the output operation of a signal from input/output terminals I/O 0-I/O 7 of the flash EEPROM, and erase enable signal EE attains a logic low level. In response to this, the flash EEPROM enters in a status polling mode in which a signal of a logic low level or a logic high level appears on input/output terminal I/O 7 in accordance with an internal circuit operation. In the status polling mode, the signal appearing on input/output terminal I/O 7 attains a logic low level when the circuit operation for data erase continues, and conversely, it attains a logic high level when the circuit operation for data erase is completed, as shown in FIG. 26(h). In this flash EEPROM, the time required for a series of operations for data erasing including the data writing into all memory cells MC in memory array 1 (erase time) is typically approximately 1 sec, which is the time period t.sub.ET from the time when erase enable signal EE attains a logic low level for definite period t.sub.EW to the time when the signal appearing on input/output terminal I/O 7 attains a logic high level in the status polling mode.
In order to ensure an operation margin in data reading, the voltage to be applied to the control gate and the drain of the memory transistor for data reading should be the voltage of 3.4 V lower than a normal supply voltage of 5 V, in erase verifying. That is, if the data reading in erase verifying is carried out by application of such a high inherent supply voltage as of approximately 5 V to the control gate of the memory transistor, the following disadvantage might occur.
More specifically, in a memory transistor which is not rendered conductive unless a gate voltage is boosted up to approximately 5 V of the inherent supply voltage, data "1" is read in erase verifying, whereas data "0" is read if the supply voltage becomes lower than the inherent level of 5 V in normal data reading. Even if this memory transistor is rendered conductive with its control gate supplied with a voltage lower than the inherent supply voltage, the transistor is not completely turned on, so that only a small amount of current flow through the bit line. This causes an increase in the time period when the data to be read by the sense amplifier becomes correct data "1" corresponding to the storage data of the transistor. That is, the access time in reading is delayed. Thus, the data reading is carried out by application of the voltage lower than the inherent supply voltage to a selected word line so that a determination is made that only a memory transistor, the threshold voltage of which is sufficiently low, is the memory transistor in which data erase is completed, in erase verifying.
Since this flash EEPROM automatically repeats the erase pulse application and the erase verifying operation in the erase mode, it requires no external control signal.
In normal data reading, address buffer 6 accepts externally applied address signals at its address terminals A0-A16 and then applies the same to row decoder 4 and column decoder 5.
As has been described heretofore, the conventional flash EEPROM repeats the cycle in which the erase pulse having a short pulse width is first applied to the memory array, and then the erase verifying is carried out, in order to prevent an excess erase. Thus, if the memory cell, in which data is not completely erased, is detected by the erase verifying operation, the erase pulse is again applied to all the memory cells in the memory array. Accordingly, the erase pulses applied again to the memory array serve to remove the electrons stored in the floating gate in data writing in the memory transistor, in which data is not yet completely erased. Conversely, the applied erase pulses serve to draw out the electrons originally existing in the floating gate therefrom in the memory transistor, in which data is already completely erased. Consequently, when the data erasing is completed with respect to memory cells in which data is less easily erased, an excess erase occurs in memory cells in which data is easily erased.
Larger the differences in easiness of data erasing between the memory cells constituting the memory array are, larger the differences in the number of erase pulses required for a complete erase of data between the memory cells constituting memory array 1 are. There is a case where the erase pulses, which are again applied so as to completely erase the data of the memory cell detected by erase verifying, cannot perform a complete data erase with respect to the memory cell, in which data is less easily erased than the detected memory cell. In this case, the erase pulses are again applied to all the memory cells in the memory array at the time when the memory cell, in which data is less easily erased, is detected by the next erase verifying operation. Therefore, as there are larger differences in easiness of data erasing between the memory cells constituting the memory array, the number of the erase pulses applied to the memory array before the data erasing is completed with respect to the memory cell, in which data is least easily erased (i.e., before the data of all the memory cells in the memory array are completely erased) increases. Thus, it is highly possible that an excess erase occurs in many memory cells when the erasing operation is completed.
The differences in easiness of data erasing between the memory cells constituting one memory array are due to various factors in the manufacture and the circuit configuration of the device, as described above. Such differences increase with an increase in the number of memory cells constituting one memory array. Therefore, a recent increase in the capacity of semiconductor memory devices, i.e., an increase in the number of bits makes the foregoing disadvantage more significant.
Incidentally, when a gate voltage is 0 V in an N channel MOS transistor, an inter-band tunneling phenomenon occurs in an overlapping region of a gate and a drain diffusion region. This phenomenon also occurs in an overlapping region of the gate and a source diffusion region when a source potential is high. The inter-band tunneling occurs When the surface of N type drain and source diffusion regions is in a deep depletion state since the gate voltage is 0 V. If the surface of these N type diffusion regions is in the deep depletion state, then an energy band at the boundary between a substrate and an oxide film beneath the gate curves sharply. Thus, electrons of a valence electron band tunnel to a conduction band in the N type diffusion regions. Holes generated at this time flow into the grounded substrate, while the electrons that have tunneled to the conduction band are focused into the N type diffusion regions. A current generated by the flow of the holes into the substrate becomes a leakage current of this N channel MOS transistor. In data erasing, since a high voltage is applied to source 230 of the memory transistor and control gate 200 is thus grounded, such an inter-band tunneling phenomenon occurs.
Referring again to FIG. 27, it is known that the inter-band tunneling phenomenon occurs at a portion 260 in the vicinity of source 230 at an interface between substrate 240 and oxide film 250, in data erasing. Since substrate 240 is grounded, the holes generated by this phenomenon flow as a leakage current to the substrate 240 side, and the electrons that have tunneled to the conduction band flow to the source 230 side together with the electrons drawn out from floating gate 210. The inter-band tunneling phenomenon in the flash EEPROM is described in the article entitled "Subbreakdown Drain Leakage Current in MOSFET", IEEE Electron Device lett., vol. EDL-8, 1987, pp. 515-517 by J. Chen et al., and the article entitled "A FLASH-ERASE EEPROM CELL WITH AN ASYMMETRIC SOURCE AND DRAIN STRUCTURE", IEEE Tech. Dig. of IEDM 1987, 25. 8, pp. 560-563 by H. Kume et al. According to these documents, a leakage current generated by the inter-band tunneling phenomenon is approximately 10.sup.-8 A for one memory transistor when the potential of source 230 is approximately 10 V. Accordingly, in the case of a 1M bit flash EEPROM, if high voltage pulses of 10 V are applied to source 230 for data erasing, then a leakage current generated in data erasing is 10 mA. This leakage current causes such various problems as heat generation of chips due to an increase in power consumption, and a decrease in supply voltage. In general, the tolerance of such a leakage current is several 10 mA or less. However, with the capacity of semiconductor apparatus having been increased in recent years, the number of memory transistors of a flash EEPROM has been increased, and the capacity of the flash EEPROM has also been increased up to approximately 16M bit at present. In the case of a 16M bit flash EEPROM, for example, if data erasing is carried out in response to high voltage pulses of 10V, then a leakage current developed in data erasing is 10 mA.times.16, i.e., 160 mA, the value largely exceeding the tolerance. Since a voltage to be applied to source 230 for data erasing is 12 V in practice, the actual magnitude of the leakage current is further larger than that value. In such a circumstance, the leakage current generated in data erasing should be reduced as much as possible.
Even if data erasing utilizing the tunnel phenomenon is carried out without the generation of the leakage current due to the inter-band tunneling phenomenon, a current generated by the drawing of electrons from floating gate 210 to source 230 becomes significantly large in each erase pulse application when a large number of memory cells are data-erased simultaneously. Therefore, from the view point of power consumption, it is desirable that the total amount of the current generated by such electron drawing in each erase pulse application is small.
As described above, with the number of memory cells constituting one memory array increasing, a problem of the increase in power consumption in data erasing becomes remarkable.